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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD1885 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 ac?7 soundmax codec functional block diagram ac97 2.1 features variable sample rate audio multiple codec configuration options external audio power-down control ac97 features ac97 2.1-compliant greater than 90 db dynamic range stereo headphone amplifier multibit converter architecture for improved s/n ratio greater than 90 db 16-bit stereo full-duplex codec four analog line-level stereo inputs for: line-in, cd, video, and aux two analog line-level mono inputs for speakerphone and pc beep mono mic input w/built-in 20 db preamp, switchable from two external sources high quality cd input with ground sense stereo line-level outputs mono output for speakerphone or internal speaker power management support 48-terminal lqfp package enhanced features full duplex variable sample rates from 7040 hz to 48 khz with 1 hz resolution jack sense pins provide automatic output switching software-enabled v refout output for microphones and external power amp split power supplies (3.3 v digital/5 v analog) mobile low-power mixer mode extended 6-bit master volume control extended 6-bit headphone volume control digital audio mixer mode phat? stereo 3d stereo enhancement soundport is a registered trademark and phat is a trademark of analog devices, inc. g a m g a m g a m sync bit_clk phat stereo g a m a m AD1885 16-bit d/a converter g = gain a = attenuate m = mute mv = master volume hv = headphone volume oscillator xtl_out xtl_in sdata_in sdata_out g a m g a m g a m 16-bit d/a converter phat stereo mmv 0db/ 20db selector pga pga 16-bit a/d converter 16-bit a/d converter sample rate generators ac link hv jack senses and eapd ctrl chip select js0/eapd js1 v refout mic1 mic2 aux cd video line_out_l mono_out line phone_in line_out_r pc_beep hp_out_r hp_out_l hv g a m nc nc v ref mv mv pop pop id0 id1 reset
C2C rev. 0 AD1885?pecifications analog input parameter min typ max unit input voltage (rms values assume sine wave input) line_in, aux, cd, video, phone_in, pc_beep 1 v rms 2.83 v p-p mic with 20 db gain (m20 = 1) 0.1 v rms 0.283 v p-p mic with 0 db gain (m20 = 0) 1 v rms 2.83 v p-p input impedance * 20 k ? input capacitance * 5 7.5 pf master volume parameter min typ max unit step size (0 db to ?4.5 db); line_out_l, line_out_r 1.5 db output attenuation range span * ?4.5 db step size (0 db to ?6.5 db); mono_out 1.5 db output attenuation range span * ?6.5 db step size (+6 db to ?8.5 db); hp_out_r, hp_out_l 1.5 db output attenuation range span * ?4.5 db mute attenuation of 0 db fundamental * 80 db programmable gain amplifier?dc parameter min typ max unit step size (0 db to 22.5 db) 1.5 db pga gain range span 22.5 db analog mixer?nput gain/amplifiers/attenuators parameter min typ max unit signal-to-noise ratio (snr) cd to line_out 90 db other to line_out 90 db step size (+12 db to ?4.5 db): (all steps tested) mic, line_in, aux, cd, video, phone_in, dac 1.5 db input gain/attenuation range: mic, line, aux, cd, video, phone_in, dac ?6.5 db step size (0 db to ?5 db): (all steps tested) pc_beep 3.0 db input gain/attenuation range: pc_beep ?5 db * guaranteed, not tested. standard test conditions unless otherwise noted temperature 25 c digital supply (dv dd ) 3.3 v analog supply (av dd ) 5.0 v sample rate (f s ) 48 khz input signal 1008 hz analog output passband 20 hz to 20 khz dac test conditions calibrated ? db attenuation relative to full scale input 0 db 10 k ? output load (line_out) 32 ? output load (hp_out) adc test conditions calibrated 0 db gain input ?.0 db relative to full scale
C3C rev. 0 AD1885 digital decimation and interpolation filters * parameter min typ max unit passband 0 0.4 f s hz passband ripple 0.09 db transition band 0.4 f s 0.6 f s hz stopband 0.6 f s hz stopband rejection ?4 db group delay 12/f s sec group delay variation over passband 0.0 s analog-to-digital converters parameter min typ max unit resolution 16 bits total harmonic distortion (thd ?4 db dynamic range (?0 db input thd+n referenced to full scale, a-weighted) 84 87 db signal-to-intermodulation distortion * (ccif method) 85 db adc crosstalk * line inputs (input l, ground r, read r; input r, ground l, read l) ?00 ?0 db line_in to other ?0 ?5 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.5 db adc offset error 5mv digital-to-analog converters parameter min typ max unit resolution 16 bits total harmonic distortion (thd) line_out ?5 db total harmonic distortion (thd) hp_out (with 10 k ? load) ?5 db dynamic range line_out (?0 db input thd+n referenced to full scale, a-weighted) 85 90 db signal-to-intermodulation distortion * (ccif method) ?00 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.7 db dac crosstalk * (input l, zero r, measure r_out; input r, zero l, measure l_out) ?0 db total audible out-of-band energy (measured from 0.6 f s to 20 khz) * ?0 db analog output parameter min typ max unit full-scale output voltage; line_out 1 v rms 2.83 v p-p output impedance * 800 ? external load impedance * 10 k ? output capacitance * 15 pf external load capacitance 100 pf full-scale output voltage; hp_out (0 db gain) 1 v rms output capacitance * 100 pf external load capacitance 32 ? v ref 2.05 2.25 2.45 v v refout 2.25 v v refout current drive 5ma mute click (muted output minus unmuted midscale dac output) 5mv * guaranteed, not tested.
C4C rev. 0 AD1885?pecifications static digital specifications * parameter min typ max unit high-level input voltage (v ih ): digital inputs 0.65 dv dd v low-level input voltage (v il ) 0.35 dv dd v high-level output voltage (v oh ), i oh = 2 ma 0.9 dv dd v low-level output voltage (v ol ), i ol = 2 ma 0.1 dv dd v input leakage current ?0 10 a output leakage current ?0 10 a power supply parameter min typ max unit power supply range?nalog (av dd ) 4.75 5.25 v power supply range?igital (dv dd ) 3.15 3.45 v power dissipation? v/3.3 v 355 mw analog supply current? v (av dd )50ma digital supply current?.3 v (dv dd )21ma power supply rejection (100 mv p-p signal @ 1 khz) * 40 db (at both analog and digital supply pins, both adcs and dacs) clock specifications parameter min typ max unit input clock frequency 24.576 mhz recommended clock duty cycle 40 50 60 % power-down mode * dv dd (3.3 v) av dd (5 v) parameter set bits typ typ unit adc pr0 20 44 ma dac pr1 20 41 ma adc and dac pr1, pr0 8 35 ma adc + dac + mixer (analog cd on) lpmix, pr1, pr0 8 26 ma mixer pr2 21 23 ma adc + mixer pr2, pr0 19 18 ma dac + mixer pr2, pr1 19 15 ma adc + dac + mixer pr2, pr1, pr0 8 10 ma analog cd only (ac-link on) lpmix, pr5, pr1, pr0 7 22 ma analog cd only (ac-link off) lpmix, pr1, pr0, pr4, pr5 0 12 ma standby pr5, pr4, pr3, pr2, pr1, pr0 0 0.1 ma headphone standby pr6 21 38 ma notes * guaranteed, not tested. output jitter is directly dependent on crystal input jitter. specifications subject to change without notice.
C5C rev. 0 AD1885 timing parameters (guaranteed over operating temperature range) parameter symbol min typ max unit reset active low pulsewidth t rst_low 1.0 s reset inactive to bit_clk startup delay t rst2clk 162.8 ns sync active high pulsewidth t sync_high 1.3 s sync low pulsewidth t sync_low 19.5 s sync inactive to bit_clk startup delay t sync2clk 162.8 ns bit_clk frequency 12.288 mhz bit_clk period t clk_period 81.4 ns bit_clk output jitter * 750 ps bit_clk high pulsewidth t clk_high 32.56 42 48.84 ns bit_clk low pulsewidth t clk_low 32.56 38 48.84 ns sync frequency 48.0 khz sync period t sync_period 20.8 s setup to falling edge of bit_clk t setup 5 2.5 ns hold from falling edge of bit_clk t hold 5ns bit_clk rise time t riseclk 2410ns bit_clk fall time t fallclk 2410ns sync rise time t risesync 2410ns sync fall time t fallsync 2410ns sdata_in rise time t risedin 2410ns sdata_in fall time t falldin 2410ns sdata_out rise time t risedout 2410ns sdata_out fall time t falldout 2410ns end of slot 2 to bit_clk, sdata_in low t s2_pdown 010ms setup to trailing edge of reset (applies to sync, sdata_out) t setup2rst 15 ns rising edge of reset to hi-z delay t off 25 ns propagation delay 15 ns reset rise time 50 ns output valid delay from rising edge of bit_clk to sdi valid 15 ns notes * output jitter is directly dependent on crystal input jitter. specifications subject to change without notice.
AD1885 C6C rev. 0 reset bit_clk t rst2clk t rst_low figure 1. cold reset sync bit_clk t sync_high t rst2clk figure 2. warm reset t clk_high bit_clk t clk_low sync t sync_high t sync_low t sync_period t clk_period figure 3. clock timing bit_clk sync t hold sdata_out t setup figure 4. data setup and hold bit_clk sync sdata_in t riseclk t risesync t risedin t risedout t fallclk t fallsync t falldin t falldout sdata_out figure 5. signal rise and fall time bit_clk sdata_out sync sdata_in slot 1 slot 2 write to 0x26 data pr4 don? care t s2_pdown note: bit_clk not to scale figure 6. ac-link low power mode timing reset sdata_out hi-z t setup2rst t off sdata_in, bit_clk figure 7. ate test mode
AD1885 C7C rev. 0 ordering guide temperature package package model range description option * AD1885jst 0 c to 70 c 48-lead lqfp st-48 * st = thin quad flatpack. environmental conditions ambient temperature rating t amb = t case ?(pd ca ) t case = case temperature in c p d = power dissipation in w ca = thermal resistance (case-to-ambient) ja = thermal resistance (junction-to-ambient) jc = thermal resistance (junction-to-case) package ja jc ca lqfp 76.2 c/w 17 c/w 59.2 c/w absolute maximum ratings * parameter min max unit power supplies digital (av dd ) ?.3 +3.6 v analog (dv dd ) ?.3 +6.0 v input current (except supply pins) 10 ma analog input voltage (signal pins) ?.3 av dd + 0.3 v digital input voltage (signal pins) ?.3 dv dd + 0.3 v ambient temperature (operating) 0 70 c storage temperature ?5 +150 c * stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in t he operational section of this specification is not implied. exposure to absolu te maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1885 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) line_out_r line_out_l cx3d rx3d filt_l filt_r afilt2 dv dd1 xtl_in xtl_out dv ss1 sdata_out bit_clk dv ss2 sdata_in dv dd2 sync afilt1 v refout v ref av ss1 AD1885 pc_beep av dd1 phone_in aux_l aux_r video_l video_r cd_l cd_gnd_ref cd_r mic1 mic2 line_in_l line_in_r mono_out av dd2 hp_out_l av ss2 hp_out_r nc av dd3 av ss3 js0 (eapd) js1 nc = no connect id1 id0 reset
C8C rev. 0 AD1885 specifications pin function descriptions digital i/o pin name lqfp i/o description xtl_in 2 i crystal (or clock) input, 24.576 mhz. xtl_out 3 o crystal output. sdata_out 5 i ac-link serial data output, AD1885 input stream. bit_ clk 6 o/i ac-link bit clock. 12.288 mhz serial data clock. daisy chain input clock. sdata_in 8 o ac-link serial data input. AD1885 output stream. sync 10 i ac-link frame sync. reset 11 i ac-link reset. AD1885 master h/w reset. chip selects pin name lqfp type description id0 45 i chip select input 0 (active low). id1 46 i chip select input 1 (active low). jack senses/eapd/general-purpose digital outputs these signals can sense the presence of audio jacks in the line-out or headphones outputs, and automatically mute the other audio outputs. js0 can also be programmed for eapd control. alternatively, both pins can be programmed as general-purpose digital out puts. pin name lqfp type description js0 47 i/o jack sense input 0 (mutes mono output). js1 48 i/o jack sense input 1 (mutes line_out and mono outputs, or line_out only). analog i/o these signals connect the AD1885 component to analog sources and sinks, including microphones and speakers. pin name lqfp i/o description pc_beep 12 i pc beep. pc speaker beep passthrough. phone_in 13 i phone input. from telephony subsystem speakerphone or handset. aux_l 14 i auxiliary input left channel. aux_r 15 i auxiliary input right channel. video_l 16 i video audio left channel. video_r 17 i video audio right channel. cd_l 18 i cd audio left channel. cd_gnd_ref 19 i cd audio analog ground reference for differential cd input. cd_ r 20 i cd audio right channel. mic1 21 i microphone 1. desktop microphone input. mic2 22 i microphone 2. second microphone input. line_in_l 23 i line in left channel. line_in_r 24 i line in right channel. line_out_l 35 o line out left channel. line_out_r 36 o line out right channel. mono_out 37 o monaural output to telephony subsystem speakerphone. hp_out_l 39 o headphones out left channel. hp_out_r 41 o headphones out right channel.
AD1885 C9C rev. 0 filter/reference these signals are connected to resistors, capacitors, or specific voltages. pin name lqfp i/o description v ref 27 o voltage reference filter. v refout 28 o voltage reference output 5 ma drive (intended for mic bias). afilt1 29 o antialiasing filter capacitor?dc right channel. aflit2 30 o antialiasing filter capacitor?dc left channel. filt_r 31 o ac-coupling filter capacitor?dc right channel. filt_l 32 o ac-coupling filter capacitor?dc left channel. rx3d 33 o 3d phat stereo enhancement?esistor. cx3d 34 i 3d phat stereo enhancement?apacitor. power and ground signals pin name lqfp type description dv dd1 1 i digital v dd 3.3 v dv ss1 4 i digital gnd dv ss2 7 i digital gnd dv dd2 9 i digital v dd 3.3 v av dd1 25 i analog v dd 5.0 v av ss1 26 i analog gnd av dd2 38 i analog v dd 5.0 v av ss2 40 i analog gnd av dd3 43 i analog v dd 5.0 v av ss3 44 i analog gnd no connects pin name lqfp type description nc 42 no connect figure 8. block diagram register map xtl_in xtl_out s 0 20 0 1 ms 0db/20db m20 0x0e ga 0x0e mcv ga 0x0c phv ga 0x10 llv rlv ga 0x12 lcv rcv ga 0x16 lav rav ga 0x14 lvv rvv m 0x10 lm m 0x12 cm m 0x16 am m 0x14 vm m 0x0e mcm m 0x0c phm d a m 0x02 lmv 0x02 mm 0x02 lmv 0x02 mm 0x04 lhv 0x04 hpm 0x04 rhv 0x04 hpm m 0x0a pcm a 0x0a pcv ls (4) rs (4) ls (3) rs (3) ls (1) rs (1) ls (2) rs (2) ls/rs (7) ls (5) ls/rs (6) rs (5) s e l e c t o r ls/rs (0) s 0x1a a b nc nc 3d 0x20 switch phat 0x20 0x22 dp phat 0x20 0x22 dp gam 0x18 lov om gam 0x18 rov om gam 0x1c liv im gam 0x1c riv im ac-link jack sense and eapd ctrl chip select js0/eapd js1 v refout mv mix 0x20 oscillators sync bit_clk sdata_out sdata_in hp_out_l mono_out phone_in video cd aux line mic2 mic1 line_out_l line_out_r hp_out_r pc_beep AD1885 g = gain a = attenuation m = mute s = selector pop pop v ref stereo mix (l) mono mix stereo mix (r) id1 id0 reset
AD1885 C10C rev. 0 product overview the AD1885 codec meets the audio codec ?7 2.1 extensions, adding support for multiple codecs and vari able sample rates. in addition, the AD1885 soundport codec is designed to meet all requirements of the audio codec ?7, component specification , revision 1.03, ?1996, intel corporation, found at www.intel.com . the AD1885 also includes other codec enhanced features such as communicating to three codecs on the same link, inte grated headphone driver and built-in phat stereo 3d enhance ment. the AD1885 is an analog front end for high-performance pc audio, modem, or dsp applications. the ac?7 architecture defines a 2-chip audio solution comprising a digital audio controller, plus a high-quality analog component that includes digital-to-analog converters (dacs), analog-to-digital con- verters (adcs), mixer, and i/o. the main architectural features of the AD1885 are the high quality analog mixer section, two channels of ? adc conver- sion, two channels of ? dac conversion and data direct scrambling (d 2 s) rate generators. functional description this section overviews the functionality of the AD1885 and is intended as a general introduction to the capabilities of the device. detailed reference information may be found in the descriptions of the indexed control registers. analog inputs the codec contains a stereo pair of ? adcs. inputs to the adc may be selected from the following analog signals: tele- phony (phone_in), mono microphone (mic1 or mic2), stereo line (line_in), auxiliary line input (aux), stereo cd rom (cd), stereo audio from a video source (video) and post-mixed stereo or mono line output (line_out). analog mixing phone_in, mic1 or mic2, line_in, aux, cd, and video can be mixed in the analog domain with the stereo output from the dacs. each channel of the stereo analog inputs may be inde- pendently gained or attenuated from +12 db to ?4.5 db in 1.5 db steps. the summing path for the mono inputs (phone_in, mic1, and mic2 to line_out and hp_out) duplicates mono chan- nel data on both the left and right line_out and hp_out. additionally, the pc attention signal (pc_beep) may be mixed with the line output and headphone. a switch allows the output of the dacs to bypass the phat stereo 3d enhancement. digital audio mode the AD1885 is designed with a digital audio mode (dam) that allows mixing of all analog inputs, independent of the dac output signal path. mixed analog input signals may be sent to the adcs for processing by the dc ?7 controller or the host, and may be used during simultaneous capture and playback at different sample rates. analog-to-digital signal path the selector sends left and right channel information to the programmable gain amplifier (pga). the pga following the selector allows independent gain control for each channel enter- ing the adc from 0 db to +22.5 db in 1.5 db steps. each channel of the adc is independent, and can process left and right channel data at different sample rates. sample rates and d 2 s the AD1885 default mode sets the codec to operate at 48 khz sample rates. the converter pairs may process left and right channel data at different sample rates. the AD1885 sample rate generator allows the codec to instantaneously change and process sample rates from 7040 hz to 48 khz with a resolution of 1 hz. the in-band integrated noise and distortion artifacts introduced by rate conversions are below ?0 db. the AD1885 uses a 4-bit ? structure and d 2 s to enhance noise immunity on mother- boards and in pc enclo sures, and to suppress idle t ones below the device? quantiz ation noise floor. the d 2 s process pushes noise and distortion artifa cts caused by errors in the multibit dac to frequencies beyond the auditory response of the human ear and then filters them. digital-to-analog signal path the analog output of the dac may be gained or attenuated from +12 db to ?4.5 db in 1.5 db steps, and summed with any of the analog input signals. the summed analog signal enters the master volume stage where each channel of the mixer out- put may be attenuated from 0 db to ?4.5 db in 1.5 db steps or muted. analog outputs the AD1885 offers a line output controlled by the master volume control and an integrated headphone driver with indep endent control. host-based echo cancellation support the AD1885 supports time correlated i/o data format by pre- senting mic data on the left channel of the adc and the mono summation of left and right output on the right channel. the adc is splittable; left and right adc data can be sampled at different rates. telephony modem support the AD1885 contains a v.34-capable analog front end for sup- porting host-based and data pump modems. the modem dac typical dynamic range is 90 db over a 4.2 khz analog output passband where f s = 12.8 khz. the left channel of the adc and dac may be used to convert modem data at the same sample rate in the range between 7040 hz and 48 khz. all pro- grammed sample rates have a resolution of 1 hz. the AD1885 supports irrational v.34 sample rates with 8/7 and 10/7 select- able multiplier coefficients. power management modes the AD1885 is designed to meet notebook and acpi power consumption requirements through flexible power management control of all internal resources. the following subsections may be independently controlled: adcs and input mux power-down dacs power-down analog mixer power-down digital interface power-down internal clocks disabled adc and dac power-down vref standby mode low-power mixer mode?d mixer alive only mode mixer bypass mode (digital audio) headphone
AD1885 C11C rev. 0 indexed control registers reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 0410h 02h master volume mm x lmv5 lmv4 lmv3 lmv2 lmv1 lmv0 x x rmv5 rmv4 rmv3 rmv2 rmv1 rmv0 8000h 04h headphones volume hpm x lhv5 lhv4 lhv3 lhv2 lhv1 lhv0 x x rhv5 rhv4 rhv3 rhv2 rhv1 rhv0 8000h 06h master volume mono mmm x x x x x x x x x x mmv mmv mmv mmv mmv 8000h 43210 08h reserved x x x x x x x x x x x x x x x x x 0ah pc beep volume pcm x x x x x x x x x x pcv3 pcv2 pcv1 pcv0 x 8000h 0ch phone in volume phm x x x x x x x x x x phv4 phv3 phv2 phv1 phv0 8008h 0eh mic volume mcm x x x x x x x x m20 x mcv4 mcv3 mcv2 mcv1 mcv0 8008h 10h line in volume lm x x llv4 llv3 llv2 llv1 llv0 x x x rlv4 rlv3 rlv2 rlv1 rlv0 8808h 12h cd volume cvm x x lcv4 lcv3 lcv2 lcv1 lcv0 x x x rcv4 rcv3 rcv2 rcv1 rcv0 8808h 14h video volume vm x x lvv4 lvv3 lvv2 lvv1 lvv0 x x x rvv4 rvv3 rvv2 rvv1 rvv0 8808h 16h aux volume am x x lav4 lav3 lav2 lav1 lav0 x x x rav4 rav3 rav2 rav1 rav0 8808h 18h pcm out volume om x x lov4 lov3 lov2 lov1 lov0 x x x rov4 rov3 rov2 rov1 rov0 8808h 1ah record select x x x x x ls2 ls1 ls0 x x x x x rs2 rs1 rs0 0000h 1ch record gain im x x x lim3 lim2 lim1 lim0 x x x x rim3 rim2 rim1 rim0 8000h 1eh reserved x x x x x x x x x x x x x x x x x 20h general purpose pop x 3d x x x mix ms lpbk x x x x x x x 0000h 22h 3d control x x x x x x x x x x x x dp3 dp2 dp1 dp0 0000h 26h power-down cntrl/stat x x pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc 000xh 28h extended audio id id1 id0 x x x x x x x x x x x x x vra 0001h 2ah extended audio stat/ctrl x x x x x x x x x x x x x x x vra 0000h 2ch/ pcm dac rate (sr1) sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h (7ah) * 32h/ pcm adc rate (sr0) sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h (78h) * 34h reserved x x x x x x x x x x x x x x x x x .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 72h jack sense/audio js1_out js0_ js1 js0 js1_ js0 js1 js0 js1 js0_ js1 js0 aud js1 js0 js 0000h interrupt/status funct out pudis pudis oe oe dis dis clr clr mode mode int int 74h serial configuration slot reg reg reg x x dhwr x x x x x x x x 7000h 16 m2 m1 m0 76h miscellaneous control dac lpmi x dam dms dlsr x alsr mod srx1 srx8 x x drsr x arsr 0404h bits z x en 0d7 d7 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 4144h 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 5360h notes all registers not shown and bits containing an x are assumed to be reserved. odd register addresses are aliased to the next lower even address. reserved registers should not be written. zeros should be written to reserved bits. * indicates aliased register for ad1819b backward compatibility.
AD1885 C12C rev. 0 reset (index 00h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 0 0h 0 0 h 0 0 h 0 0h 0 0t e s e rt e s e r t e s e r t e s e rt e s e rx x x x x4 e s4 e s 4 e s 4 e s4 e s3 e s3 e s 3 e s 3 e s3 e s2 e s2 e s 2 e s 2 e s2 e s1 e s1 e s 1 e s 1 e s1 e s0 e s0 e s 0 e s 0 e s0 e s9 d i9 d i 9 d i 9 d i9 d i8 d i8 d i 8 d i 8 d i8 d i7 d i7 d i 7 d i 7 d i7 d i6 d i6 d i 6 d i 6 d i6 d i5 d i5 d i 5 d i 5 d i5 d i4 d i4 d i 4 d i 4 d i4 d i3 d i3 d i 3 d i 3 d i3 d i2 d i2 d i 2 d i 2 d i2 d i1 d i1 d i 1 d i 1 d i1 d i0 d i0 d i 0 d i 0 d i0 d ih 0 1 4 0h 0 1 4 0 h 0 1 4 0 h 0 1 4 0h 0 1 4 0 note: writing any value to this register per forms a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration). reading this register returns the id code of the part and a code for the type of 3 d stereo enhancement. id[9:0] identify capability. the id decodes the capabilities of AD1885 based on the following: bit = 1 function AD1885 id0 dedicated mic pcm in channel 0 id1 modem line codec support 0 id2 bass and treble control 0 id3 simulated stereo (mono to stereo) 0 id4 headphone out support 1 id5 loudness (bass boost) support 0 id6 18-bit dac resolution 0 id7 20-bit dac resolution 0 id8 18-bit adc resolution 0 id9 20-bit adc resolution 0 se[4:0] stereo enhancement. the 3d stereo enhancement identifies the analog devices 3d stereo enhancement. master volume registers (index 02h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 2 0h 2 0 h 2 0 h 2 0h 2 0 r e t s a mr e t s a m r e t s a m r e t s a mr e t s a m e m u l o ve m u l o v e m u l o v e m u l o ve m u l o v m mm m m m m mm mx x x x x5 v m l5 v m l 5 v m l 5 v m l5 v m l4 v m l4 v m l 4 v m l 4 v m l4 v m l3 v m l3 v m l 3 v m l 3 v m l3 v m l2 v m l2 v m l 2 v m l 2 v m l2 v m l1 v m l1 v m l 1 v m l 1 v m l1 v m l0 v m l0 v m l 0 v m l 0 v m l0 v m lx x x x xx x x x x5 v m r5 v m r 5 v m r 5 v m r5 v m r4 v m r4 v m r 4 v m r 4 v m r4 v m r3 v m r3 v m r 3 v m r 3 v m r3 v m r2 v m r2 v m r 2 v m r 2 v m r2 v m r1 v m r1 v m r 1 v m r 1 v m r1 v m r0 v m r0 v m r 0 v m r 0 v m r0 v m rh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 rmv[5:0] right master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of ?4.5 db. lmv[5:0] l eft master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of ?4.5 db. mm master volume mute. when this bit is set to ?,?the channel is muted. mm xmv5 . . . xmv0 function 0 00 0000 0 db attenuation 0 01 1111 ?6.5 db attenuation 0 11 1111 ?4.5 db attenuation 1 xx xxxx db attenuation
AD1885 C13C rev. 0 headphones volume registers (index 04h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 4 0h 4 0 h 4 0 h 4 0h 4 0e m u l o v s e n o h p d a e he m u l o v s e n o h p d a e h e m u l o v s e n o h p d a e h e m u l o v s e n o h p d a e he m u l o v s e n o h p d a e hm p hm p h m p h m p hm p hx x x x x5 v h l5 v h l 5 v h l 5 v h l5 v h l4 v h l4 v h l 4 v h l 4 v h l4 v h l3 v h l3 v h l 3 v h l 3 v h l3 v h l2 v h l2 v h l 2 v h l 2 v h l2 v h l1 v h l1 v h l 1 v h l 1 v h l1 v h l0 v h l0 v h l 0 v h l 0 v h l0 v h lx x x x xx x x x x5 v h r5 v h r 5 v h r 5 v h r5 v h r4 v h r4 v h r 4 v h r 4 v h r4 v h r3 v h r3 v h r 3 v h r 3 v h r3 v h r2 v h r2 v h r 2 v h r 2 v h r2 v h r1 v h r1 v h r 1 v h r 1 v h r1 v h r0 v h r0 v h r 0 v h r 0 v h r0 v h rh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 rhv[5:0] right headphone volume control. the least significant bit represents 1.5 db. this register controls the out- put from +6 db to a maximum attenuation of ?8.5 db. lhv[5:0] left headphone volume control. the least significant bit represents 1.5 db. this register controls the output from +6 db to a maximum attenuation of ?8.5 db. hpm headphone volume mute. when this bit is set to ?,?the channel is muted. hpm xhv5 . . . xhv0 function 0 00 0000 6 db gain 0 01 1111 ?0.5 db attenuation 0 11 1111 ?8.5 db attenuation 1 xx xxxx db attenuation master volume mono (index 06h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 0h 6 0 h 6 0 h 6 0h 6 0 e m u l o v r e t s a me m u l o v r e t s a m e m u l o v r e t s a m e m u l o v r e t s a me m u l o v r e t s a m o n o mo n o m o n o m o n o mo n o m m m mm m m m m m m m mm m mx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x4 v m m4 v m m 4 v m m 4 v m m4 v m m3 v m m3 v m m 3 v m m 3 v m m3 v m m2 v m m2 v m m 2 v m m 2 v m m2 v m m1 v m m1 v m m 1 v m m 1 v m m1 v m m0 v m m0 v m m 0 v m m 0 v m m0 v m mh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 mmv[4:0] mono master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. mmm mono master volume mute. when this bit is set to ?,?the channel is muted. pc beep register (index 0ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 0h a 0 h a 0 h a 0h a 0e m u l o v p e e b _ c pe m u l o v p e e b _ c p e m u l o v p e e b _ c p e m u l o v p e e b _ c pe m u l o v p e e b _ c pm c pm c p m c p m c pm c px x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x3 v c p3 v c p 3 v c p 3 v c p3 v c p2 v c p2 v c p 2 v c p 2 v c p2 v c p1 v c p1 v c p 1 v c p 1 v c p1 v c p0 v c p0 v c p 0 v c p 0 v c p0 v c px x x x xh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 pcv[3:0] pc beep volume control. the least significant bit represents 3 db attenuation. this register controls the output from 0 db to a maximum attenuation of ?5 db. the pc beep is routed to left and right line outputs even when AD1885 is in a reset state. this is so that power-on self-test (post) codes can be heard by the user in case of a hardware problem with the pc. pcm pc beep mute. when this bit is set to ?,?the channel is muted. pcm pcv3 . . . pcv0 function 0 0000 0 db attenuation 0 1111 ?5 db attenuation 1 xxxx db attenuation
AD1885 C14C rev. 0 phone volume (index 0ch) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h c 0h c 0 h c 0 h c 0h c 0e m u l o v e n o h pe m u l o v e n o h p e m u l o v e n o h p e m u l o v e n o h pe m u l o v e n o h pm h pm h p m h p m h pm h px x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x4 v h p4 v h p 4 v h p 4 v h p4 v h p3 v h p3 v h p 3 v h p 3 v h p3 v h p2 v h p2 v h p 2 v h p 2 v h p2 v h p1 v h p1 v h p 1 v h p 1 v h p1 v h p0 v h p0 v h p 0 v h p 0 v h p0 v h ph 8 0 0 8h 8 0 0 8 h 8 0 0 8 h 8 0 0 8h 8 0 0 8 phv[4:0] phone volume. allows setting the phone volume attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. phm phone mute. when this bit is set to ?,?the channel is muted. mic volume (index 0eh) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h e 0h e 0 h e 0 h e 0h e 0 c i mc i m c i m c i mc i m e m u l o ve m u l o v e m u l o v e m u l o ve m u l o v m c mm c m m c m m c mm c mx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x0 2 m0 2 m 0 2 m 0 2 m0 2 mx x x x x4 v c m4 v c m 4 v c m 4 v c m4 v c m3 v c m3 v c m 3 v c m 3 v c m3 v c m2 v c m2 v c m 2 v c m 2 v c m2 v c m1 v c m1 v c m 1 v c m 1 v c m1 v c m0 v c m0 v c m 0 v c m 0 v c m0 v c mh 8 0 0 8h 8 0 0 8 h 8 0 0 8 h 8 0 0 8h 8 0 0 8 mcv[4:0] mic volume gain. allows setting the mic volume attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. m20 microphone 20 db gain block 0 = disabled; gain = 0 db 1 = enabled; gain = 20 db. mcm mic mute. when this bit is set to ?,?the channel is muted. line in volume (index 10h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 0 1h 0 1 h 0 1 h 0 1h 0 1e m u l o v n i e n i le m u l o v n i e n i l e m u l o v n i e n i l e m u l o v n i e n i le m u l o v n i e n i lm lm l m l m lm lx x x x xx x x x x4 v l l4 v l l 4 v l l 4 v l l4 v l l3 v l l3 v l l 3 v l l 3 v l l3 v l l2 v l l2 v l l 2 v l l 2 v l l2 v l l1 v l l1 v l l 1 v l l 1 v l l1 v l l0 v l l0 v l l 0 v l l 0 v l l0 v l lx x x x xx x x x xx x x x x4 v l r4 v l r 4 v l r 4 v l r4 v l r3 v l r3 v l r 3 v l r 3 v l r3 v l r2 v l r2 v l r 2 v l r 2 v l r2 v l r1 v l r1 v l r 1 v l r 1 v l r1 v l r0 v l r0 v l r 0 v l r 0 v l r0 v l rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rlv[4:0] right line in volume. allows setting the line in right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. llv[4:0] line in volume left. allows setting the line in left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lm line in mute. when this bit is set to ?,?the channel is muted. cd volume (index 12h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 2 1h 2 1 h 2 1 h 2 1h 2 1e m u l o v d ce m u l o v d c e m u l o v d c e m u l o v d ce m u l o v d cm v cm v c m v c m v cm v cx x x x xx x x x x4 v c l4 v c l 4 v c l 4 v c l4 v c l3 v c l3 v c l 3 v c l 3 v c l3 v c l2 v c l2 v c l 2 v c l 2 v c l2 v c l1 v c l1 v c l 1 v c l 1 v c l1 v c l0 v c l0 v c l 0 v c l 0 v c l0 v c lx x x x xx x x x xx x x x x4 v c r4 v c r 4 v c r 4 v c r4 v c r3 v c r3 v c r 3 v c r 3 v c r3 v c r2 v c r2 v c r 2 v c r 2 v c r2 v c r1 v c r1 v c r 1 v c r 1 v c r1 v c r0 v c r0 v c r 0 v c r 0 v c r0 v c rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rcv[4:0] right cd volume. allows setting the cd right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lcv[4:0] left cd volume. allows setting the cd left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. cvm cd volume mute. when this bit is set to ?,?the channel is muted.
AD1885 C15C rev. 0 video volume (index 14h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 4 1h 4 1 h 4 1 h 4 1h 4 1e m u l o v o e d i ve m u l o v o e d i v e m u l o v o e d i v e m u l o v o e d i ve m u l o v o e d i vm vm v m v m vm vx x x x xx x x x x4 v v l4 v v l 4 v v l 4 v v l4 v v l3 v v l3 v v l 3 v v l 3 v v l3 v v l2 v v l2 v v l 2 v v l 2 v v l2 v v l1 v v l1 v v l 1 v v l 1 v v l1 v v l0 v v l0 v v l 0 v v l 0 v v l0 v v lx x x x xx x x x xx x x x x4 v v r4 v v r 4 v v r 4 v v r4 v v r3 v v r3 v v r 3 v v r 3 v v r3 v v r2 v v r2 v v r 2 v v r 2 v v r2 v v r1 v v r1 v v r 1 v v r 1 v v r1 v v r0 v v r0 v v r 0 v v r 0 v v r0 v v rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rvv[4:0] right video volume. allows setting the video right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lvv[4:0] left video volume. allows setting the video left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. vm video mute. when this bit is set to ?,?the channel is muted. aux volume (index 16h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 1h 6 1 h 6 1 h 6 1h 6 1e m u l o v x u ae m u l o v x u a e m u l o v x u a e m u l o v x u ae m u l o v x u am am a m a m am ax x x x xx x x x x4 v a l4 v a l 4 v a l 4 v a l4 v a l3 v a l3 v a l 3 v a l 3 v a l3 v a l2 v a l2 v a l 2 v a l 2 v a l2 v a l1 v a l1 v a l 1 v a l 1 v a l1 v a l0 v a l0 v a l 0 v a l 0 v a l0 v a lx x x x xx x x x xx x x x x4 v a r4 v a r 4 v a r 4 v a r4 v a r3 v a r3 v a r 3 v a r 3 v a r3 v a r2 v a r2 v a r 2 v a r 2 v a r2 v a r1 v a r1 v a r 1 v a r 1 v a r1 v a r0 v a r0 v a r 0 v a r 0 v a r0 v a rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rav[4:0] right aux volume. allows setting the aux right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lav[4:0] left aux volume. allows setting the aux left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. am aux mute. when this bit is set to ?,?the channel is muted. pcm out volume (index 18h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 8 1h 8 1 h 8 1 h 8 1h 8 1 t u o m c pt u o m c p t u o m c p t u o m c pt u o m c p e m u l o ve m u l o v e m u l o v e m u l o ve m u l o v m om o m o m om ox x x x xx x x x x4 v o l4 v o l 4 v o l 4 v o l4 v o l3 v o l3 v o l 3 v o l 3 v o l3 v o l2 v o l2 v o l 2 v o l 2 v o l2 v o l1 v o l1 v o l 1 v o l 1 v o l1 v o l0 v o l0 v o l 0 v o l 0 v o l0 v o lx x x x xx x x x xx x x x x4 v o r4 v o r 4 v o r 4 v o r4 v o r3 v o r3 v o r 3 v o r 3 v o r3 v o r2 v o r2 v o r 2 v o r 2 v o r2 v o r1 v o r1 v o r 1 v o r 1 v o r1 v o r0 v o r0 v o r 0 v o r 0 v o r0 v o rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rov[4:0] right pcm out volume. allows setting the pcm right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lov[4:0] left pcm out volume. allows setting the pcm left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. om pcm out volume mute. when this bit is set to ?,?the channel is muted. volume table xm x4 . . . x0 function 0 00000 +12 db gain 0 01000 0 db gain 0 11111 ?4.5 db gain 1 xxxxx db gain
AD1885 C16C rev. 0 record select control register (index 1ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 1h a 1 h a 1 h a 1h a 1t c e l e s d r o c e rt c e l e s d r o c e r t c e l e s d r o c e r t c e l e s d r o c e rt c e l e s d r o c e rx x x x xx x x x xx x x x xx x x x xx x x x x2 s l2 s l 2 s l 2 s l2 s l1 s l1 s l 1 s l 1 s l1 s l0 s l0 s l 0 s l 0 s l0 s lx x x x xx x x x xx x x x xx x x x xx x x x x2 s r2 s r 2 s r 2 s r2 s r1 s r1 s r 1 s r 1 s r1 s r0 s r0 s r 0 s r 0 s r0 s rh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 rs[2:0] right record select ls[2:0] left record select. used to select the record source independently for right and left. see table for legend. the default value is 0000h, which corresponds to mic in. rs2 . . . rs0 right record source 0 mic 1 cd_r 2 video_r 3 aux_r 4 line_in_r 5 stereo mix (r) 6 mono mix 7 phone_in ls2 . . . ls0 left record source 0 mic 1 cd_l 2 video_l 3 aux_l 4 line_in_l 5 stereo mix (l) 6 mono mix 7 phone_in record gain (index 1ch) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h c 1h c 1 h c 1 h c 1h c 1n i a g d r o c e rn i a g d r o c e r n i a g d r o c e r n i a g d r o c e rn i a g d r o c e rm im i m i m im ix x x x xx x x x xx x x x x3 m i l3 m i l 3 m i l 3 m i l3 m i l2 m i l2 m i l 2 m i l 2 m i l2 m i l1 m i l1 m i l 1 m i l 1 m i l1 m i l0 m i l0 m i l 0 m i l 0 m i l0 m i lx x x x xx x x x xx x x x xx x x x x3 m i r3 m i r 3 m i r 3 m i r3 m i r2 m i r2 m i r 2 m i r 2 m i r2 m i r1 m i r1 m i r 1 m i r 1 m i r1 m i r0 m i r0 m i r 0 m i r 0 m i r0 m i rh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 rim[3:0] right input mixer gain control. each lsb represents 1.5 db, 0000 = 0 db and the range is 0 db to +22.5 db. lim[3:0] left input mixer gain control. each lsb represents 1.5 db, 0000 = 0 db and the range is 0 db to +22.5 db. im input mute. 0 = unmuted, 1 = muted or db gain. im xim3 . . . xim0 function 0 1111 +22.5 db gain 0 0000 0 db gain 1 xxxxx db gain
AD1885 C17C rev. 0 general-purpose register (index 20h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 0 2h 0 2 h 0 2 h 0 2h 0 2e s o p r u p - l a r e n e ge s o p r u p - l a r e n e g e s o p r u p - l a r e n e g e s o p r u p - l a r e n e ge s o p r u p - l a r e n e gp o pp o p p o p p o pp o px x x x xd 3d 3 d 3 d 3d 3x x x x xx x x x xx x x x xx i mx i m x i m x i mx i ms ms m s m s ms mk b p lk b p l k b p l k b p lk b p lx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 note: this register should be read before writing to generate a mask for only the bit(s) that need to be changed. lpbk loopback control. adc/dac digital loopback mode ms mic select 0 = mic1 1 = mic2. mix mono output select 0 = mix 1 = mic. 3d 3d phat stereo enhancement 0 = phat stereo is off. 1 = phat stereo is on. pop pcm output path and mute. the pop bit controls the optional pcm out 3d bypass path (the pre- and post-3d pcm out paths are mutually exclusive). 0 = pre-3d 1 = post-3d. 3d control register (index 22h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 2 2h 2 2 h 2 2 h 2 2h 2 2l o r t n o c d 3l o r t n o c d 3 l o r t n o c d 3 l o r t n o c d 3l o r t n o c d 3x x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x3 p d3 p d 3 p d 3 p d3 p d2 p d2 p d 2 p d 2 p d2 p d1 p d1 p d 1 p d 1 p d1 p d0 p d0 p d 0 p d 0 p d0 p dh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 dp[2:0] depth control. sets 3d ?epth?phat stereo enhancement according to table below. dp3 . . . dp0 depth 0000 0% 0001 6.67% .. .. 14 93.33% 15 100%
AD1885 C18C rev. 0 subsection ready register (index 26h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 2h 6 2 h 6 2 h 6 2h 6 2t a t s / l r t n c n w o d - r e w o pt a t s / l r t n c n w o d - r e w o p t a t s / l r t n c n w o d - r e w o p t a t s / l r t n c n w o d - r e w o pt a t s / l r t n c n w o d - r e w o pd p a ed p a e d p a e d p a ed p a e6 r p6 r p 6 r p 6 r p6 r p5 r p5 r p 5 r p 5 r p5 r p4 r p4 r p 4 r p 4 r p4 r p3 r p3 r p 3 r p 3 r p3 r p2 r p2 r p 2 r p 2 r p2 r p1 r p1 r p 1 r p 1 r p1 r p0 r p0 r p 0 r p 0 r p0 r px x x x xx x x x xx x x x xx x x x xf e rf e r f e r f e rf e rl n al n a l n a l n al n ac a dc a d c a d c a dc a dc d ac d a c d a c d ac d ah x 0 0 0h x 0 0 0 h x 0 0 0 h x 0 0 0h x 0 0 0 note: the ready bits are read only, writing to ref, anl, dac, adc will have no effect. these bits indicate the status for the AD1885 subsections. if the bit is a one, then that subsection is ready .?ready is defined as the subsection able to perform in its nom inal state. adc adc section ready to transmit data. dac dac section ready to accept data. anl analog gainuators, attenuators, and mixers ready. ref voltage references, vref and vrefout up to nominal level. pr[5:0] AD1885 power-down modes. the first three bits are to be used individually rather than in combinat ion with each other. the last bit pr3 can be used in combination with pr2 or by itself. the mixer and reference cannot be powered down via pr3 unless the adcs and dacs are also powered down. nothing else can be powered up until the reference is up. pr0 ?power-down adc pr1 ?power-down dac pr2 ?power-down analog mixer pr3 ?power-down v ref and v refout pr4 ?power-down ac-link pr5 ?power-down internal clock pr6 ?power-down headphone eapd ?external amp power-down control signal pr5 has no effect unless all adcs, dacs, and the ac-link are powered down. the reference and the mixer can either be up or down, but all power-up sequences must be allowed to run to completion before pr5 and pr4 are both set. in multiple-codec systems, the master codec? pr5 and pr4 bits control the slave codec. pr5 is also effective in the slave codec if the master? pr5 bit is clear, but the pr4 bit has no effect except to enable or disable pr5. power-down state eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 adc power-down x 0 0 0 0 0 0 1 dac power-down x 0 0 0 0 0 1 0 adc and dac power-down x 0 0 0 0 0 1 1 mixer power-down x 0 0 0 0 1 0 0 adc + mixer power-down x 0 0 0 0 1 0 1 dac + mixer power-down x 0 0 0 0 1 1 0 adc + dac + mixer power-down x 0 0 0 0 1 1 1 standby x 1 1 1 1 1 1 1 extended audio id register (index 28h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 8 2h 8 2 h 8 2 h 8 2h 8 2d i o i d u a d e d n e t x ed i o i d u a d e d n e t x e d i o i d u a d e d n e t x e d i o i d u a d e d n e t x ed i o i d u a d e d n e t x e1 d i1 d i 1 d i 1 d i1 d i0 d i0 d i 0 d i 0 d i0 d ix x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xa r va r v a r v a r va r vh 1 0 0 0h 1 0 0 0 h 1 0 0 0 h 1 0 0 0h 1 0 0 0 note: the extended audio id is a read only register. vra variable rate audio. vra = 1 indicates support for variable rate audio. id[1:0] id1, id0 is a 2-bit field that indicates the codec configuration: primary is 00; secondary is 01.
AD1885 C19C rev. 0 extended audio status and control register (index 2ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 2h a 2 h a 2 h a 2h a 2l r t c / t s o i d u a d e d n e t x el r t c / t s o i d u a d e d n e t x e l r t c / t s o i d u a d e d n e t x e l r t c / t s o i d u a d e d n e t x el r t c / t s o i d u a d e d n e t x ex x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xa r va r v a r v a r va r vh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 note: the extended audio status and control register is a read/write register that provides status and control of the extended audio features. vra variable rate audio. vra = 1 enables support for variable rate audio mode (sample rate control registers and slotreq signaling). pcm dac rate register (index 2ch) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d ) h a 7 ( / h c 2) h a 7 ( / h c 2 ) h a 7 ( / h c 2 ) h a 7 ( / h c 2) h a 7 ( / h c 2e t a r c a d m c pe t a r c a d m c p e t a r c a d m c p e t a r c a d m c pe t a r c a d m c p5 1 r s5 1 r s 5 1 r s 5 1 r s5 1 r s4 1 r s4 1 r s 4 1 r s 4 1 r s4 1 r s3 1 r s3 1 r s 3 1 r s 3 1 r s3 1 r s2 1 r s2 1 r s 2 1 r s 2 1 r s2 1 r s1 1 r s1 1 r s 1 1 r s 1 1 r s1 1 r s0 1 r s0 1 r s 0 1 r s 0 1 r s0 1 r s9 r s9 r s 9 r s 9 r s9 r s8 r s8 r s 8 r s 8 r s8 r s7 r s7 r s 7 r s 7 r s7 r s6 r s6 r s 6 r s 6 r s6 r s5 r s5 r s 5 r s 5 r s5 r s4 r s4 r s 4 r s 4 r s4 r s3 r s3 r s 3 r s 3 r s3 r s2 r s2 r s 2 r s 2 r s2 r s1 r s1 r s 1 r s 1 r s1 r s0 r s0 r s 0 r s 0 r s0 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 2ch is an alias for 7ah. the vra bit in register 2ah must be set for the alias to work; if a zero is written to vra, both sample rates are reset to 48 khz. sr[15:0] writing to this register allows programming of the sampling frequency from 7040 hz (1b 80h) to 48 khz (bb80h) in 1 hz increments. programming a value outside of the range 7040 hz (1b80h) to 48000 hz (bb80h) causes the codec to saturate. for all rates, if the value written to the register is supported, that value will be echoed back when read, otherwise the closest rate supported is returned. pcm adc rate register (index 32h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d ) h 8 7 ( / h 2 3) h 8 7 ( / h 2 3 ) h 8 7 ( / h 2 3 ) h 8 7 ( / h 2 3) h 8 7 ( / h 2 3e t a r c d a m c pe t a r c d a m c p e t a r c d a m c p e t a r c d a m c pe t a r c d a m c p5 1 r s5 1 r s 5 1 r s 5 1 r s5 1 r s4 1 r s4 1 r s 4 1 r s 4 1 r s4 1 r s3 1 r s3 1 r s 3 1 r s 3 1 r s3 1 r s2 1 r s2 1 r s 2 1 r s 2 1 r s2 1 r s1 1 r s1 1 r s 1 1 r s 1 1 r s1 1 r s0 1 r s0 1 r s 0 1 r s 0 1 r s0 1 r s9 r s9 r s 9 r s 9 r s9 r s8 r s8 r s 8 r s 8 r s8 r s7 r s7 r s 7 r s 7 r s7 r s6 r s6 r s 6 r s 6 r s6 r s5 r s5 r s 5 r s 5 r s5 r s4 r s4 r s 4 r s 4 r s4 r s3 r s3 r s 3 r s 3 r s3 r s2 r s2 r s 2 r s 2 r s2 r s1 r s1 r s 1 r s 1 r s1 r s0 r s0 r s 0 r s 0 r s0 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 32h is an alias for 78h. the vra bit in register 2ah must be set for the alias to work; if a zero is written to vra, both sample rates are reset to 48 khz. sr[15:0] writing to this register allows programming of the sampling frequency from 7040 hz (1b 80h) to 48 khz (bb80h) in 1 hz increments. programming a value outside of the range 7040 hz (1b80h) to 48000 hz (bb80h) causes the codec to saturate. for all rates, if the value written to the register is supported, that value will be echoed back when read; otherwise, the closest rate supported is returned. jack sense/audio interrupt/status register (index 72h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 2 7h 2 7 h 2 7 h 2 7h 2 7 o i d u a / e s n e s k c a jo i d u a / e s n e s k c a j o i d u a / e s n e s k c a j o i d u a / e s n e s k c a jo i d u a / e s n e s k c a j s u t a t s / t p u r r e t n is u t a t s / t p u r r e t n i s u t a t s / t p u r r e t n i s u t a t s / t p u r r e t n is u t a t s / t p u r r e t n i / t u o _ 1 s j/ t u o _ 1 s j / t u o _ 1 s j / t u o _ 1 s j/ t u o _ 1 s j t c n u ft c n u f t c n u f t c n u ft c n u f _ 0 s j_ 0 s j _ 0 s j _ 0 s j_ 0 s j t u ot u o t u o t u ot u o 1 s j1 s j 1 s j 1 s j1 s j s i d u ps i d u p s i d u p s i d u ps i d u p 0 s j0 s j 0 s j 0 s j0 s j s i d u ps i d u p s i d u p s i d u ps i d u p 1 s j1 s j 1 s j 1 s j1 s j_ _ _ _ _ e oe o e o e oe o 0 s j0 s j 0 s j 0 s j0 s j_ _ _ _ _ e oe o e o e oe o 1 s j1 s j 1 s j 1 s j1 s j s i ds i d s i d s i ds i d 0 s j0 s j 0 s j 0 s j0 s j s i ds i d s i d s i ds i d 1 s j1 s j 1 s j 1 s j1 s j r l cr l c r l c r l cr l c 0 s j0 s j 0 s j 0 s j0 s j r l cr l c r l c r l cr l c 1 s j1 s j 1 s j 1 s j1 s j e d o me d o m e d o m e d o me d o m 0 s j0 s j 0 s j 0 s j0 s j e d o me d o m e d o m e d o me d o m d u ad u a d u a d u ad u a t n it n i t n i t n it n i 1 s j1 s j 1 s j 1 s j1 s j0 s j0 s j 0 s j 0 s j0 s j s js j s j s js j t n it n i t n i t n it n i h 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 note: all register bits are read/write except for audint, jsint, js0 and js1, which are read only . jsint indicates that a jack sense interrupt has been generated by js0 or js1. remains set until all js enabled interrupts are cleared. js0 indicates pin js0 state. js1 indicates pin js1 state. audint indicates the codec has generated audio interrupt. remains set until software clears all pending interrupts. js0mode sets js0 pin input mode, 1 = interrupt 0 = jack sense. js1mode sets js1 pin input mode, 1 = interrupt 0 = jack sense. js0clr this bit is set by the codec when there is a pending js0 interrupt. software must clear this bit to clear the js0 interrupt status bit. js1clr this bit is set by the codec when there is a pending js1 interrupt. software must clear this bit to clear the js1 interrupt status bit. js0dis if the js0dis bit is set, the codec ignores jack sense pin js0. js1dis if the js1dis bit is set, the codec ignores jack sense pin js1.
AD1885 C20C rev. 0 js0_oe enables js0 pin as a general-purpose output. js1_oe enables js1 pin as a general-purpose output. js0pudis setting the js0pudis bit disables the js0 pin internal pull-up. js1pudis setting the js1pudis bit disables the js1 pin internal pull-up. js0_out when enabled as gpo, the js0 pin reflects the state of the js0_out bit. js1_out/funct when enabled as gpo, the js1 pin reflects the state of the js1_out bit, otherwise this bit can be set to change the functionality of js1 so that only line_out is muted when js1 is high. serial configuration (index 74h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 4 7h 4 7 h 4 7 h 4 7h 4 7 l a i r e sl a i r e s l a i r e s l a i r e sl a i r e s n o i t a r u g i f n o cn o i t a r u g i f n o c n o i t a r u g i f n o c n o i t a r u g i f n o cn o i t a r u g i f n o c t o l st o l s t o l s t o l st o l s 6 16 1 6 1 6 16 1 2 m g e r2 m g e r 2 m g e r 2 m g e r2 m g e r1 m g e r1 m g e r 1 m g e r 1 m g e r1 m g e r0 m g e r0 m g e r 0 m g e r 0 m g e r0 m g e rx x x x xx x x x xr w h dr w h d r w h d r w h dr w h dx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x note: this register is not reset when the reset register (register 00h) is written. dhwr disable hardware reset. regm0 master codec register mask. regm1 slave 1 codec register mask. regm2 slave 2 codec register mask. slot16 enable 16-bit slots. if your system uses only a single AD1885, you can ignore the register mask. slot16 makes all ac-link slots 16 bits in length, formatted into 16 slots. miscellaneous control bits (index 76h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 7h 6 7 h 6 7 h 6 7h 6 7s t i b l o r t n o c c s i ms t i b l o r t n o c c s i m s t i b l o r t n o c c s i m s t i b l o r t n o c c s i ms t i b l o r t n o c c s i m c a dc a d c a d c a dc a d z z z z z i m p li m p l i m p l i m p li m p l x x x x x x x x x xm a dm a d m a d m a dm a ds m ds m d s m d s m ds m dr s l dr s l d r s l d r s l dr s l dx x x x xr s l ar s l a r s l a r s l ar s l a d o md o m d o m d o md o m n en e n e n en e 0 1 x r s0 1 x r s 0 1 x r s 0 1 x r s0 1 x r s 7 d7 d 7 d 7 d7 d 8 x r s8 x r s 8 x r s 8 x r s8 x r s 7 d7 d 7 d 7 d7 d x x x x xx x x x xr s r dr s r d r s r d r s r dr s r dx x x x xr s r ar s r a r s r a r s r ar s r ah 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 arsr adc right sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch). drsr dac right sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch). srx8d7 multiply sr1 rate by 8/7. srx10d7 multiply sr1 rate by 10/7. srx10d7 and srx8d7 are mutually exclusive. moden modem filter enable (left channel only). change only when dacs and adcs are powered down. alsr adc left sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch). dlsr dac left sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch). dms digital mono select. 0 = mixer 1 = left dac and right dac. dam digital audio mode. dac outputs bypass analog mixer and sent directly to the codec output. lpmix low power mixer. dacz zero fill (vs. repeat) if dac is starved for data.
AD1885 C21C rev. 0 sample rate 0 (index 78h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 8 7 / ) h 2 3 (h 8 7 / ) h 2 3 ( h 8 7 / ) h 2 3 ( h 8 7 / ) h 2 3 (h 8 7 / ) h 2 3 (0 e t a r e l p m a s0 e t a r e l p m a s 0 e t a r e l p m a s 0 e t a r e l p m a s0 e t a r e l p m a s5 1 0 r s5 1 0 r s 5 1 0 r s 5 1 0 r s5 1 0 r s4 1 0 r s4 1 0 r s 4 1 0 r s 4 1 0 r s4 1 0 r s3 1 0 r s3 1 0 r s 3 1 0 r s 3 1 0 r s3 1 0 r s2 1 0 r s2 1 0 r s 2 1 0 r s 2 1 0 r s2 1 0 r s1 1 0 r s1 1 0 r s 1 1 0 r s 1 1 0 r s1 1 0 r s0 1 0 r s0 1 0 r s 0 1 0 r s 0 1 0 r s0 1 0 r s9 0 r s9 0 r s 9 0 r s 9 0 r s9 0 r s8 0 r s8 0 r s 8 0 r s 8 0 r s8 0 r s7 0 r s7 0 r s 7 0 r s 7 0 r s7 0 r s6 0 r s6 0 r s 6 0 r s 6 0 r s6 0 r s5 0 r s5 0 r s 5 0 r s 5 0 r s5 0 r s4 0 r s4 0 r s 4 0 r s 4 0 r s4 0 r s3 0 r s2 0 r s2 0 r s 2 0 r s 2 0 r s2 0 r s1 0 r s1 0 r s 1 0 r s 1 0 r s1 0 r s0 0 r s0 0 r s 0 0 r s 0 0 r s0 0 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 32h is an alias for 78h. the vra bit in register 2ah must be set for the alias to w ork; if a zero is written to vra, both sample rates are reset to 48 khz. sr0[15:0] writing to this register allows the user to program the sampling frequency from 7 khz (1b58h) to 48 khz (bb80h) in 1 hertz increments. programming a value greater than 48 khz or less than 7 khz may cause unpredictable results. sample rate 1 (index 7ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 7 / ) h c 2 (h a 7 / ) h c 2 ( h a 7 / ) h c 2 ( h a 7 / ) h c 2 (h a 7 / ) h c 2 (1 e t a r e l p m a s1 e t a r e l p m a s 1 e t a r e l p m a s 1 e t a r e l p m a s1 e t a r e l p m a s5 1 1 r s5 1 1 r s 5 1 1 r s 5 1 1 r s5 1 1 r s4 1 1 r s4 1 1 r s 4 1 1 r s 4 1 1 r s4 1 1 r s3 1 1 r s3 1 1 r s 3 1 1 r s 3 1 1 r s3 1 1 r s2 1 1 r s2 1 1 r s 2 1 1 r s 2 1 1 r s2 1 1 r s1 1 1 r s1 1 1 r s 1 1 1 r s 1 1 1 r s1 1 1 r s0 1 1 r s0 1 1 r s 0 1 1 r s 0 1 1 r s0 1 1 r s9 1 r s9 1 r s 9 1 r s 9 1 r s9 1 r s8 1 r s8 1 r s 8 1 r s 8 1 r s8 1 r s7 1 r s7 1 r s 7 1 r s 7 1 r s7 1 r s6 1 r s6 1 r s 6 1 r s 6 1 r s6 1 r s5 1 r s5 1 r s 5 1 r s 5 1 r s5 1 r s4 1 r s4 1 r s 4 1 r s 4 1 r s4 1 r s3 1 r s2 1 r s2 1 r s 2 1 r s 2 1 r s2 1 r s1 1 r s1 1 r s 1 1 r s 1 1 r s1 1 r s0 1 r s0 1 r s 0 1 r s 0 1 r s0 1 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 2ch is an alias for 7ah. the vra bit in register 2ah must be set for the alias to work; if a zero is written to vra, both sample rates are reset to 48 khz. sr1[15:0] writing to this register allows the user to program the sampling frequency from 7 khz (1b58h) to 48 khz (bb80h) in 1 hertz increments. p rogramming a value greater than 48 khz or less than 7 khz may cause unpredictable results. vendor id registers (index 7ch?h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h c 7h c 7 h c 7 h c 7h c 71 d i r o d n e v1 d i r o d n e v 1 d i r o d n e v 1 d i r o d n e v1 d i r o d n e v7 f7 f 7 f 7 f7 f6 f6 f 6 f 6 f6 f5 f5 f 5 f 5 f5 f4 f4 f 4 f 4 f4 f3 f3 f 3 f 3 f3 f2 f2 f 2 f 2 f2 f1 f1 f 1 f 1 f1 f0 f0 f 0 f 0 f0 f7 s7 s 7 s 7 s7 s6 s6 s 6 s 6 s6 s5 s5 s 5 s 5 s5 s4 s4 s 4 s 4 s4 s3 s3 s 3 s 3 s3 s2 s2 s 2 s 2 s2 s1 s1 s 1 s 1 s1 s0 s0 s 0 s 0 s0 sh 4 4 1 4h 4 4 1 4 h 4 4 1 4 h 4 4 1 4h 4 4 1 4 s[7:0] this register is ascii encoded to ?. f[7:0] this register is ascii encoded to ?. g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h e 7h e 7 h e 7 h e 7h e 72 d i r o d n e v2 d i r o d n e v 2 d i r o d n e v 2 d i r o d n e v2 d i r o d n e v7 t7 t 7 t 7 t7 t6 t6 t 6 t 6 t6 t5 t5 t 5 t 5 t5 t4 t4 t 4 t 4 t4 t3 t3 t 3 t 3 t3 t2 t2 t 2 t 2 t2 t1 t1 t 1 t 1 t1 t0 t0 t 0 t 0 t0 t7 v e r7 v e r 7 v e r 7 v e r7 v e r6 v e r6 v e r 6 v e r 6 v e r6 v e r5 v e r5 v e r 5 v e r 5 v e r5 v e r4 v e r4 v e r 4 v e r 4 v e r4 v e r3 v e r3 v e r 3 v e r 3 v e r3 v e r2 v e r2 v e r 2 v e r 2 v e r2 v e r1 v e r1 v e r 1 v e r 1 v e r1 v e r0 v e r0 v e r 0 v e r 0 v e r0 v e rh 0 6 3 5h 0 6 3 5 h 0 6 3 5 h 0 6 3 5h 0 6 3 5 t[7:0] this register is ascii encoded to ?. rev[7:0] revision register field contains the revision number. these bits are read-only and should be verified before accessing vendor defined features.
AD1885 C22C rev. 0 applications circuits the AD1885 has been designed to require a minimum amount of external circuitry. the recommended applications circuits are shown in figures 9?8. reference designs for the AD1885 are available and may be obtained by contacting your local analog devices sales representative or authorized distributor. example shell programs for establishing a communications path between the AD1885 and an adsp-21xx or adsp-21xxx are also available. figure 9. recommended one-codec pwr/decoupling and ac97 connections line_out_r line_out_l cx3d rx3d filt_l filt_r afilt2 afilt1 vrefout vref avss1 avdd1 phone_in aux_l aux_r video_l video_r cd_l cd_gnd_ref cd_r mic1 mic2 line_in_l line_in_r AD1885 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 44 45 46 47 48 + av d d nc nc nc 47nf + + av d d 270pf npo 270pf npo + 47pf pc_beep 22pf 22pf 24.576mhz + dvdd note: if not used, ground jack sense pins. note: all unused analog inputs (line_in_l/r, aux_l/r, video_l/r, mic1, mic2, pc_beep, phone_in and cd_l/r/gnd) must be left unconnected. fb 600z 10k dvdd1 xtl_in xtl_out dvss1 sdata_out bit_clk dvss2 sdata_in dvdd2 sync reset pc_beep js1 jso/eapd id1 id0 avss3 avdd3 nc hp_out_r avss2 ho_out_l avdd2 mono_out sdata_out sdata_in sync reset bit_clk
AD1885 C23C rev. 0 jack sense operation the AD1885 features two jack sense pins (js0 and js1) that can be used to automatically mute the line_ out and/or mono_out audio outputs. when the jack sense pins are connected to the output jacks, the AD1885 can sense whether an audio plug has been inserted into a particular output jack and automatically mute the other unnecessary audio outputs. the js1 pin should normally be connected to the hp_out jack to automatically mute the mono_out and line_out audio signals, while the js0 pin should normally be connected to the line_out jack to automatically mute the mono_out signal. it is also possible to set the d15 bit in the jack sense index register (72h), which causes js1 to only m ute the line_out signal. this option may be desirable in certain audio configurations. table i summarizes the jack sense operation. table i. jack sense operation table hp_out plug line_out plug audio output states audio output states (js1) (js0) (reg 72h, d15 = 0) (reg 72h, d15 = 1) out out hp_out = on hp_out = on line_out = on line_out = on mono_out = on mono_out = on out in hp_out = on hp_out = on line_out = on line_out = on mono_out = mute mono_out = mute in out hp_out = on hp_out = on line_out = mute line_out = mute mono_out = mute mono_out = on in in hp_out = on hp_out = on line_out = mute line_out = mute mono_out = mute mono_out = mute note: plug in = jack sense high, plug out = jack sense low. the jack sense inputs are active high and their functionality is enabled by default on codec power-up. if necessary, the jack s ense inputs can be individually disabled by writing to the d8 and d9 bits on the codec jack sense index register (72h). the jack sense pins contain active internal pull-ups. if the jack sense inputs are not being used, they should be pulled down t o digital ground using 10 k ? resistors. this prevents line_out and mono_out from becoming muted while the jack senses are enabled. connecting the jack senses to the output jacks headphone jack the diagram on fi gure 10 shows the preferred method to connect the js1 jack sense line to the hp_out jack. t his scheme requires a stereo jack with a n ormally closed and isolated single switch. the switch holds the jack sense line low (grounded) until an audio plug is inserted, causing the switch to open and the jack sense line to go high due to the codec internal pull-up. the r2 and r 3 resistors keep the electrolytic output caps properly polarized while the hp_out jack is not used. l1 600z l2 600z c4 470pf c1 470pf optional emc components isolated nc switch + + note: locate r1 close to codec. jack sense line to codec js1 (pin 48) from codec hp_out_r (pin 41) from codec hp_out_l (pin 39) headphone out 5 4 3 2 1 figure 10. jack sense connection to hp_out jack, using isolated switch alternatively, when an audio output jack containing an isolated switch is not available, the circuit shown on figure 11 can be used. while the audio plug is out, this circuit keeps the jack sense line state low, by the pull-down affect of r2 (with no audio pre sent) or by tracking the lower peaks of the hp_out audio signal. once an audio plug is inser ted and the jack switch opens, the jack sense line switches to a high state due to the codec internal pull-up, which quickly charges c1 to dvdd. the r2 and r3 resistors also keep the electrolytic output caps properly polarized while the hp_out jack is not used.
AD1885 C24C rev. 0 l1 600z l2 600z c4 470pf optional emc components + + note: locate r1 and c1 close to codec. jack sense to codec js1 (pin 48) from codec hp_out_r (pin 41) from codec hp_out_l (pin 39) headphone out 1 2 3 4 5 j1 c5 470pf d1 mmbd914 figure 11. jack sense connection to hp_out jack, using nonisolated switch line_ out jack although not shown, if a line_out jack is used and the jack sense functionality is desired, the line_out jack should be wired in a similar configuration as shown above for the hp_out jack (preferably figure 10). the line_out jack should normally be connected to the js0 input, in order to mute the mono_out signal. we recommend that in this case the output coupling caps (c2, c3) be set to 2.2 f. all other values should be kept the same. application circuits cd-rom connections typical cd-rom drives generate 2 v rms output and re quire a voltage divider for compatibility with the codec input (1 v rms range). the recommended circuit is basically a group of divide-by-two voltage dividers as shown on figure 12. the cd_gnd_ref pin is used to cancel differential ground noise from the cd-rom. for optimum noise cancellation, this sec- tion of the divider should have approximately half the impedance of the right and left channel section dividers. 1 2 3 4 header for cd rom audio (lggr) voltage divider ac-coupling to codec cd_l input to codec cd_gnd_ref input to codec cd_r input figure 12. typical cd-rom audio connections line_in, aux and video input connections most of these audio sources also generate 2 v rms audio level and require a ? db input voltage divider to be compatible with the codec inputs. figure 13 shows the recommended application circuit. for applications requiring emc compliance, the emc com- ponents should be configured and selected to provide adequate rf immunity and emissions control. voltage divider ac-coupling to codec right channel input to codec left channel input line/aux/video input 1 2 3 4 5 j1 emc components c1 470pf c2 470pf l2 600z l1 600z figure 13. line_in, aux, and video input connections
AD1885 C25C rev. 0 microphone connections the AD1885 contains an internal microphone preamp with 20 db gain; in most cases a direct microphone connection as shown in figure 14 is adequate. if the microphone level is too low, an external preamp can be added as shown in figure 15. in either cas e the microphone bias can be derived from the codec? internal reference (v refout ) using a 2.2 k ? resi stor. for the preamp circuit, the v refout signal can also provide the midpoint bias for the amplifier. to meet the pc99 1.0a requirements, the mic signal s hould be placed on the microphone jack tip and the bias on the ring. this configuration supports electret microphones with three conductor plugs, as well as dynamic microphones with two conductor plugs (ring and sleeve shorted together). additional filtering may be required to limit the microphone response to the audio band of interest. ac-coupling to codec mic1 or mic2 input from codec vrefout mic input 1 2 3 4 5 j1 emc components c1 470pf c2 470pf l2 600z l1 600z mic bias figure 14. recommended microphone input connections 4 to codec mic1 or mic2 input from codec vrefout ac-coupling mic input 1 2 3 4 5 j1 emc components c1 470pf c2 470pf l2 600z l1 600z mic bias av d d u1 preamp ad8531 figure 15. microphone with additional external preamp (20 db gain) line output connections the AD1885 codec provides stereo line_out signals at a standard 1 v rms level. these signals must be ac-coupled before they can be connected to an external load. after the ac-coupling, a minimal resistive load is recommend to keep the ca pacit ors properly biased and reduce click and pop when plugging stereo equipment into the output jack. the capacitor values sh ould be selected to provide a desired frequency response, taking into account the nominal impedance of the external load. to meet the pc99 specific a- tion for pcs, testing must be performed with a 10 k ? load, therefore a 1 f value is recommended to achieve less than ? db roll-off at 20 hz. from codec line_out_r from codec line_out_l ac-coupling j1 emc components c2 470pf c1 470pf l1 600z l2 600z stereo line_out jack note: if an output amp is used, the ac-coupling cap values will dependend on the amp design. figure 16. recommended line_out connections
AD1885 C26C rev. 0 pc_beep input connections the recommended pc_beep input circuit is shown below. u nder most cases the pc_beep signal should be attenuated, filtered and then ac-coupled into the codec. to codec pc_beep input pc_beep (from ich) figure 17. recommended pc_beep connections grounding and layout to reduce noise and emissions, analog devices recommends a split ground plane as shown in figure 18. the purpose of splitting the ground plane is to create a low noise analog area that is somewhat isolated from the digital ground current noise generated by the system? logic. all the analog circuitry should be placed on the analog ground plane area. for reference purposes, and to return power supply currents, the analog and digital ground planes must be connected at some poi nt, ideally a small bridge under or near the codec should be provided. a 0 ? resistor or a ferrite bead should also be considered since these allow some flexibility in optimizing the layout to meet emc requirements. pin 1 isolation trench connect split ground planes at or near codec. analog ground plane digital ground plane AD1885 figure 18. recommended split ground plane analog power supply to minimize audio noise, the codec analog power supply (avdd) should be well decoupled and regulated. in pc systems it is rec- ommended that the analog supply be derived from the 12 v pc power supply using a localized linear voltage regulator. preferabl y, the analog power supply should be connected to the codec? analog section using a ferrite bead. if a power plane layer is being used in the system design, it is recommended that the analog power plane for the codec also be split (mirroring the analog ground plane). in this case, the analog power su pply ferrite bead should bridge the isolation trench, close to the codec location.
AD1885 C27C rev. 0 outline dimensions dimensions shown in inches and (mm). 48-lead thin plastic quad flatpack (lqfp) (st-48) 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.011 (0.27) 0.006 (0.17) 0.019685 (0.5) bsc 0.354 (9.00) bsc seating plane 0.063 (1.60) max 0 min 0 7 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09) printed in u.s.a. c00753C2.5C7/00 (rev. 0)

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